COEN 180
Homework 3
HW1 HW2 HW3 HW4 HW5 HW6 HW7 HW8


Figure 1: 3T DRAM Cell


Figure 1 gives the design of an earlier DRAM technology. The bit is stored as the presence or the absence of a charge on the line between M1 and M2 (marked by a dot).

For a read operation, we precharge the Read Column Line to Vcc and then drive the Read Row Line to Vcc. This turns M3 on. If there is a sufficient charge between M1 and M2, then M2 is open and the voltage in the Read Column Line drops towards GND. If there is no charge between M1 and M2, then M2 is closed. In this case, there is no drop in voltage on the Read Column Line.

  1. Describe in detail the write operation to this DRAM cell.
  2. Explain why this design is dynamic? (Why does the cell need periodic refreshing in order to maintain the stored bit?).
  3. Explain why this design is technically inferior to the design of the 1T1C DRAM cell.

  1. Refreshing a DRAM array is accomplished by sequentially opening each row in the DRAM. Assume a 64 Mb DRAM is organized as a 16M · 4 array with 4 bits of input and output. Assume that the memory array is organized as a square with the same number of column and row addresses. (Recall that the cells in a row are refreshed at the same time.) Assume that the rows need to be refreshed every 64 msec and that the read cycle time is 100 nsec. Calculate the percentage of time that the DRAM is busy refreshing.

  1. SRAM is used in the design of graphics memory. What is the amount of data that a high resolution device can consume? Specify your assumptions.
© 2003 Thomas Schwarz, S.J., COEN, SCU                                                                              SCU            COEN            T. Schwarz            COEN 180