COEN 180
Homework 5
HW1 HW2 HW3 HW4 HW5 HW6 HW7 HW8

Due Monday, May 12


  1. (Related to ABET criteria: Contemporary Issues)
    Describe in brief the function of Mangetoresistiv Random Access Memory (1 paragraph). What are the potentials of MRAM, what are the technological challenges? (1 paragraph). Cite your resources. Some places to start out at are given below.
    James M. Daughton, NVE Corporation: Advanced MRAM Concepts, 2001
    James M. Daughton, NVE Corporation: Magnetoresistive Random Access Memory, 2000
    David Voss: Instant Access Memory, Wired, April 2000
  2. Simplified Cache Performance Model: CPU time can be divided into the clock cycles that the CPU spends executing the program and the clock cycles the CPU spends waiting for the memory system. Thus:

    CPU time = (CPU execution clock cycles + Memory stall clock cycles)

    We assume that hits in the cache are counted as CPU execution clock cycles. Memory stall clock cycles result from the number of memory accesses per program, miss penalty (measured in clock cycles), and miss rate. Since read and writes have different performance, we need to separate their effects. Calculate the number of clock cycles per instruction for the following three scenarios involving a CISC machine:

    1. No caching:
      • cycles per instruction 7.3
    2. Write-through Caching:
      • cycles per instruction 7.3
      • 2.1 reads per instruction
      • 0.7 writes per instruction
      • read miss rate is 11%
      • read miss penalty is 5 cycles.
      • all write operations cost 2 cycles.
    3. Copy-Back Caching:
      • cycles per instruction 7.3
      • 2.1 reads per instruction
      • 0.7 writes per instruction
      • read miss rate is 11%
      • read miss penalty is 5 cycles.
      • write miss rate is 5%.
      • write miss penalty is 3 cycles.
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