Figure 1: Storage Transistor with Floating Gate.
The floating gate is completely surrounded by an isolation layer. This enables the floating gate transistor to be used as non-volatile memory, but also imposes the need to find ways to charge or discharge it.
In a FAMOST (floating gate avalanche injection MOS transistor), the isolation layer is impermeable only to low energy electrons, but can be passed by high energy electrons. A pulse of about 20V is applied between the word line and the bit line (control gate and drain) for about 50ms. This accumulates in the channel region between drain and sink hot (fast) charge carriers, that have enough energy to pass the isolation region between the substrate and the floating gate. This accumulates a charge on the floating gate. We cannot reverse the voltage in order to remove the charge from the floating gate. To erase the charge, this type of transistor is subjected to UV radiation which in a few minutes is absorbed by most of the charge carriers in the floating gate. They have sufficiently high energy to escape through the insulation layer.
This type of device is used in so-called EPROM (erasable programmable read only memory). For writing, an EPROM programmer is available. For erasure, an EPROM chip has a quartz window, through which UV radiation can be applied.
The next generation of floating gate transistors use a thin layer of gate oxide between the floating gate and the channel region of the substrate. Charging the floating gate is done by the same method, a 50ms long 20V pulse that draws electrons from the channel region through the thin layer of gate oxide into the floating gate. For discharging, we can now apply an inverse voltage of 20V, that moves the charge from the floating gate into the channel region. If we were to apply the inverse voltage for too long, then we would move electrons from the control gate into the floating gate, hence, we do not do that.
Flash memory is built from floating gate transistors without a different programming / erasure voltage. Several main mechanisms are available to move charge carriers through the tunnel oxide layer, namely Polyoxide Conduction, CHEI (Channel hot electron injection) and the high electric field Fowler-Nordheim tunneling.
Fowler-Nordheim tunneling is a quantum-mechanical process in which a particle can pass through a classically (as in pre-quantum mechanics physics) forbidden region. To make use of the Fowler-Nordheim effect, we need to apply a strong injection field acorss the oxide. The strength of the field can be achieved by either thin oxide layers (so that the voltage can remain small), or by using oxides grown from polycrystalline silicon (which have a rough surface that leads to electric field variations and hence enhanced tunneling of the electrons). An alternative (CHEI) to tunneling is providing electrons with high energy to pass from the channel into the floating gate. This implies providing a high voltage differential between the drain and the control gate. Current flash memories use either FN tunneling (involving the construction of thin oxide layers) or use hot electron insertion (involving a higher voltage of e.g. 5-20V).
Increasing the number of programming-erasing cycles and the density of flash memory remain flash memory design challenges.
Flash memory arrays strive for a very compact layout. A large variety of different designs, using either F-N or CHE for programming, have arisen, and compete at the market place. Read access is done rapidly using conventual circuitry for access and readout. However, erasure and writing are very slow operations. To overcome these limitations, flash memories are subdivided into blocks, allowing erasing and writing to be done at the block level. Erasure is usually performed for a complete block, hence the name "flash". Internal registers and buffers provide temporary storage for pages of data. A charge pump circuit is required to provide the high internal voltages needed for erase and write operations.
Figure 2: NOR array layout of flash memory. (SL source lines, (BL bit lines, WL word lines)
Figure 2 gives a basic "NOR array" arrangement for flash memory. To read a cell, we assert a single word line. The source lines are asserted and the assertion or deassertion of a bit line gives the contents of the storage cells in the same row.
Figure 3 gives the principal possibilities of erasing a NOR cell as well as the principal method of writing it..
Figure 3: NOR cell erasure methods and program methods:
( Upper Left High Voltage Source Erase, Upper Right: Negative Gate Source Erase, Lower Left: Channel Erase, Lower Right: Programming)
The NAND cell is reduced to the NOR cell design. A typical NAND array has a unit block typically formed by 16 NAND cells (Figure 4 only shows 8) cells in series with two select transistors, the ground select transistor (GSL) and the bit line select transistor (SSL). The NAND cell has a threshold voltage higher than 0V if it is programmed and a negative threshold voltage in the erased state. In a read operation, the cell to be read has a grounded selected word line, whereas the other cells in the array have the unselected level of 4.5 V. The other cells are hence conductive. If the selected cell is programmed, then the voltage in the word line is too low to make the cell conductive, if it is erased, then it is conductive. Programming is achieved through F-N tunneling of the electrons in the channel to the floating gate. This is accomplished by applying a high voltage (18 - 20 V) on the word line and grounding the substrate. Erasure uses F-N tunneling as well. The substrate is charged with 19 - 21 V and the control gate is grounded.
The NAND architecture has excellent densities, but slow read times, which makes it more appropriate to storage applications.
Figure 4: NAND Array
By tightly controlling the charge of the floating gate, it is even possible to store two bits per single cell. The different bit values 00, 01, 10, 11 correspond to different charges on the floating gate and hence to different threshold voltages. A read can for example succeeds by comparing the current in the bitline with those emanating from reference cells. Figure 5 shows such a scheme, in which the level from the bitline is compared to those of three reference lines. The reference cells are biased so that their threshold voltages V1, V2, V3 divide the possible threshold voltage Vt of a memory cell into 4 different zones: Vt < V1 < V2 < V3 (a value of 00); V1 < Vt < V2 < V3 (a value of 01), V1 < V2 < Vt < V3 (a value of 10); and V1 < V2 < V3 < Vt ( a value of 11). If the threshold voltage of a reference cell is smaller than the threshold voltage of the memory cell, then the current emanating from the reference cell is smaller then the current emanating from the memory cell. The data stored in the cell are thus read by comparing the currents. The sense amplifiers pull up the difference in currents and a decoder then puts out the value of the stored data in the cell. An alternative is to linearly raise the voltage of the control gate to determine from the number of steps the threshold voltage of the cell and hence the stored value. The key concern in designing the read process is the tradeoff between speed and accuracy.
Writing at multi-level presents the same principal challenge. In principle, the voltage differentials and the timing determine the floating gate charge, however, in practise some form of monitoring is needed. Charge retention also becomes a problem with multilevel memories, since now smaller changes in the charge of the floating gate lead to a miss-read.
Figure 5: Decoding of Multilevel Cells
|© 2003 Thomas Schwarz, S.J., COEN, SCU SCU COEN T. Schwarz COEN 180|