|Overview SRAM Cell Design SRAM Layout Advanced SRAM Design|
Figure 1: 4 Transistor and 2 Resistor SRAM Cell Design
Figure 2: 6 Transistor SRAM Cell Design
The 4T+2R design contains four transistors and two resistors. The resistors R1 and T2 divide the voltage between VCC and ground. If T2 is in high impedance state, then the voltage differential falls off almost entirely at T2, so that the connection between R1 and T2 is at VCC voltage. If this is the case, then T3 is enabled and therefore in low impedance state. As a consequence, the voltage level between R2 and T3 is close to ground. This in turn disables T2, which remains in high impedance. If however T2 is in low impedance, then the roles of T2 and T3 are reversed. We have seen, that there exist two stable states, one with T2 in high impedance and one with T3 in high impedance.
Transistors T1 and T4 lead to two complimentary bit lines. If they are enabled, then one of the bit lines will be driven to VCC and the other one to GND. This allows reading of the SRAM cell. If one of them is driven to VCC and the other one to GND, and if then the transistors T1 and T4 are enabled and then disabled, the SRAM cell will stay in the state imposed on it by the bit lines. This is the write process of the SRAM cell.
The 4T2R design has a certain amount of current leakage on the lines from ground to VCC. For this reason, we can use transistors in lieu of the resistors. The resistors R1 and R2 are replaced by the transistors T5 and T6. Notice that if T2 is open, then T5 is closed and vice versa. The same applies to the pair T3 and T6. The resistance between GND and VCC is therefore always high and only a minute current will flow. The basic function of the SRAM cell remains: it has two stable states, one where T2 is open and one where T2 is closed. Read and write operations function as before.
Figure 3: SRAM Array (256K x 4b). (RD = Row Decoder, SA = Sense Amplifiers)
Figure 3 gives the outline of a 256K • 4b SRAM array. The inputs/outputs to the chip are (1) Chip Enable, (2) Write Enable, (3) 4 bits of input (4) 4 bits of output, and (5) 16 bits of address. The addresses are split into two groups of 8 bits. Each group is the input to an 8 to 28 decoder.
Read Operation: The column address decoder selects one of 28 word lines. Each column of 28 SRAM cells sends its output to the sense amplifiers. The two bitlines emanating from an SRAM cell are complementary. The sense amplifiers pull up the differential between the bit lines to full voltage differential. The row decoder then selects one quartet of the outputs of the sense amplifiers. The output is then gated out of the chip.
Write Operation: The data is gated to the Write Driver, which generates input to all the rows in Figure 3 (columns in Figure 4). The column decoder selects the pair of bit lines that are driven. The row decoder enables a row of SRAM cells. The SRAM cells in this row that are not selected by the column decoder receive merely their own stored bit as the output value. The four SRAM cells in the row that are selected will be flipped to the new input.
Figure 4: SRAM Array
To provide faster memory devices, we can switch to a faster technology, use tighter technology, or even a different semiconductor like GaAs. Other factors influencing speed are the power supply voltage (higher voltage results in faster operations but uses up more energy, important for mobile applications), cool the circuit, or even change the pinout in order to reduce noise.
The primary architectural device to increase speeds is to introduce pipelining. Strictly speaking, pipelining only decreases the times between accesses, and does not lower individual random access times. The addition of a latch for input and output can improve the system control of memory.
Figure 5 shows the timing of an asynchronous SRAM. Addresses are valid for a time tRC. When a valid address apears on the address pins of an SRAM, then the data appears after time tAA. However, for time tCH the data for the previous access is still valid. Notice that there is a time where the data out lines do not have valid data. Since there are no control signals that indicate when the data is valid, the reading device has to sample at time tAA + 1/2 tv. If we try to sample the data out line earlier, then we run the danger of reading invalid data.
We can improve the reliability and speed of the SRAM by latching the data
Figure 5: Asynchronous SRAM Timing
|© 2003 Thomas Schwarz, S.J., COEN, SCU SCU COEN T. Schwarz COEN 180|